PP logo


Sine-wave burst generator.



The BG01 is a simple fixed-frequency sine-wave burst generator designed for applications where you need a high peak voltage with low RMS value.
One particular application is measurement of the peak output current of a power amplifier by increasing the level slowly and watching the amplifier output signal on an oscilloscope (Note: Any use is on your own risk).
Another possible application is time alignment of drivers in a multi-way loudspeaker system, but this may require modifications to the circuit.
As the primary application for this circuit is to display a waveform on an oscilloscope, all calibration instructions assume you have access to an oscilloscope with a bandwidth of approximately 100 times the sine-wave frequency or more.

Block Schematic.

BG01 block schematic.
Fig.1: BG01 Block Schematic.

Fig. 1 shows the 6 blocks of BG01:

1A sine-wave oscillator with a fixed 4.8 Vpp output level.
The THD should be below 5% so the output will look like a sine-wave on an oscilloscope.
The primary purpose of the "SINE" output is to be able to calibrate the sine-wave level, but it may be useful for other purposes.
2A zero-cross detector that clocks the counter and makes sure that level changes occur at the zero-cross of the sine-wave so DC and clicks on the output are avoided.
3A counter with a fixed on time of 1 period and an off time selectable from 1 to 255 periods to set the pulse / pause ratio.
The "TRIG" output from the counter is a fixed 5 V pulse that is used to trig the oscilloscope.
4An adjustable attenuator to set the pulse and pause levels and a switch to select between them.
The pulse level can be set from 0 to 20 Vpp and the pause level from 0 to 0.5 times the pulse level.
5An output amplifier that will deliver 20 Vpp into 2 kΩ.
6a voltage regulator.

BG01 output waveforms.
Fig.2: BG01 Output Waveforms with a pause time of 9 periods.

Sine Wave Oscillator.

Simple Wien Bridge Oscillator Schematic.
Fig.3: Simple 1 kHz Wien Bridge Oscillator.

The Wien bridge oscillator is a very simple circuit that oscillates at the frequency where the phase shift from U1B's output to its non-inverting input is 0 degrees and the total loop-gain in the circuit is 1.
At this frequency, the voltage gain from U1B's output to its non-inverting input is 1/3, so the gain from U1B's non-inverting input to its output must be 3 to maintain oscillation.
As the values of C and R have tolerances, the gain via the Wien bridge will be slightly different than 1/3 (0.28 to 0.38 with 1% resistors and 20% capacitors).
The values for R3, R4 and R5 takes this, their own tolerances and frequency dependent gain of U1B into account and the circuit should work up to 20 kHz.
If you use resistors with 5% tolerances, use 10 kΩ, 8.2 kΩ and 3.3 kΩ for R3, R4 and R5.

The circuit around U1C is a simple amplifier to increase the 2.5 Vpp on U1B's output to the 4.8 Vpp needed on the "SINE" output.
In addition C11 and R13 forms a simple low-pass filter at half the oscillator frequency. This reduces the 2. and 3. harmonic of the output frequency and thereby the THD by a factor of 2.

If you want another frequency than 1 kHz, the component values are:
Keep R in the range 3 kΩ to 50 kΩ.
The sheet "Components" in BG01B_Calc.ods ( part of the download later ) can be used to calculate new component values.

Zero-cross Detector.

Zero-cross detector schematic.
Fig.4: Zero-cross detector.

A zero-cross detector should be very simple: an OP-AMP with one input connected to the signal and the other input on GND. It does not work.
An OP-AMP is generally not a very good comparator as can be seen from the ZCA waveform plot in Fig. 5 below. The delay from the actual zero-crossing until the output has changed is almost 10us in the simulation plot (the measured value is 6.2 µs).
In this case the solution is to add an offset to the signal as we have a well known input signal with a fixed slew-rate around the zero-crossing.
R24 and R25 adds approximately 0.5 V to the input signal and R21 adjusts the reference signal for the comparator.

BG01 zero-cross detector waveforms.
Fig.5: Zero-cross detector waveforms (split x-axis). 0 to 0.1 ms is the start of the pulse and 1.0 ms to 1.1 ms is the end of the pulse.

LimeV(sine)Input sine wave.
BlueV(zca)ZC output with U1D connected without offset.
RedV(zcb)ZC output with U1D connected with offset.
Cyan10*V(bursta)Output from burst generator with U1D connected without offset. The amplitude is magnified by 10 and the trace is offset by -2 V for clarity. It is obvious from this plot that change in level does not happen at the zero-crossing.
Magenta10*V(burstb)Output from burst generator with schematic shown. The amplitude is magnified by 10 and the trace is offset by -4 V for clarity.

The zero-cross detector is most easily adjusted with R21 by observing the waveform on the "BURST" output. This adjustment must be done after the oscillator amplitude has been adjusted.

Counter and Logic.

Counter and Logic schematic.
Fig.6: Counter and Logic.

Counter waveforms.
Fig.7: Counter waveforms with a pause time of 8 cycles.

The signal from the zero-cross detector goes into Schmitt-trigger U3C. The output from the zero-cross detector is around ±12 V and is clamped to GND by the internal diode in U3C and to VDD by D31. D31 is required when an AHC series gate is used as these do not have a clamp-diode to VDD. If a HC series gate is used, D31, D32 and D33 are not needed (AHC132 is used here because I have them). R31 limits the current to around 120 µA.
The output from the zero-cross detector has a rise-time of around 15 µs while the maximum recommended rise-time for U2's CP input is 500 ns, so U3 must be a Schmitt-trigger.

74HC40103 is an 8-bit down-counter with a single output (TC) which is low when the count is zero. When the PE input is low, the data on P7..P0 pins are loaded into the counter as an initial count value. I fig. 6, the PE input is connected to the TC output, so when the count is 0, the counter will reload the value set by the jumpers J31..J38.
The number of pause periods from the burst-generator is the same as the binary value on P7..P0.
If you want one pulse, then 12 pause periods, P7..P0 must be set to 00001100, so jumpers J33, J34 must be installed. With no jumpers installed, output will be constant at pulse level.

The logic around U3B, U3D, U3E selects the operating mode based on jumpers J39, J40:

Not installedNot installedNormal burst mode.
Not installedInstalledPulse level output for calibration.
InstalledNot installedPause level output for calibration.
InstalledInstalledIllegal mode (output is pause level).

Attenuator, Analog Switch and Output Amplifier.

Attenuator, Analog Switch and Output Amplifier schematic.
Fig.8: Attenuator, Analog Switch and Output Amplifier.

Trimmers R61 and R63 sets the PULSE and PAUSE levels.
Capacitors C62 and C63 ac-couples the signals from the trimmers into the FET-switches. As the impedance in this point changes with the setting of R61 and R63, these capacitors must be very large to maintain the signals on the FET-switch inputs in-phase.
R64, R66, R68, R69 sets the DC level on the inputs of the switches (U4) to VDD/2.
R65, R67 limits the current into the FET switches in case the output from the oscillator exceeds 5 Vpp.
U1E buffers the output signal from the switches and adds 6.5 times gain for an output signal of up to 20 Vpp that is the maximum the TL074 is guaranteed to deliver into 2 kΩ.

Voltage Regulator.

Voltage Regulator schematic.
Fig.9: Voltage Regulator.

C81..C84, R82, R83 is a simple filter for the OP-AMP.
D81, R81 is a 5 V zener regulator for VDD. If you use a supply voltage other than ±15 V, change R81 so the current through it is around 10 mA.

External control connections.

In some cases it is desirable to be able to select the generator settings with front panel controls rather than using jumpers and trimmers.
The board has terminals for external Level and Pause potmeters (a complete schematic is in the download)

Pulse/pause switch connection.

Fig.10: Mode switch. The switch can be a 3-position toggle or rotary switch.

Pause switch connection.

Fig.11: Pulse/pause ratio selector. The switch can be a 6 or 8-position rotary switch. It must be a make-before-break type to avoid full output level during switching (or you must remember to set the mode to Pause Level before switching).

Level potmeter connection.

Fig.12: Level and pause level potmeter connection (replaces R61 and R63 on the PCB). The Level potmeter sets the level for both the pulse and pause while the Pause potmeter sets the ratio between them.

Level potmeter connection.

Fig.13: Alternate potmeter connection (replaces R61 and R63 on the PCB). The Level potmeter sets the level for the pulse while the Pause potmeter sets the level for the pause signal.


The specification for the burst-generator measured on the prototype.

Output frequency975 Hz
"SINE" output level1.5 V (4.3 Vpp)
"SINE" output THD1.8%
"BURST" output maximum pulse level9.3 V (26 Vpp)
"BURST" output maximum pause level4.5 V (13 Vpp)
"TRIG" output level0 V / 5 V
Output resistance100 Ω
Minimum recommended output load impedance2 kΩ
Supply voltage± 15 V
Supply current+ 19 / - 8 mA
Board size (length / width / height)84.6 mm / 55.9 mm / 12.5 mm

Table 2: Specification for BG01B.


Photo of mounted board.
Fig.14: Photo of mounted board.

Download BG01B design files.

I have boards available for this project. See the PCBs page.

Known Issues / updates.

Currently no known issues.

Copyright and disclaimer.

Copyright Notice.
This web-page, including but not limited to all text, drawings and photos, is the intellectual property of Poul Petersen, and is Copyright ©.
Reproduction or re-publication by any means whatsoever is strictly prohibited under International Copyright laws.
The author grants the reader the right to use this information for personal use only.
Any commercial use is prohibited without express written authorization from Poul Petersen.

The information is provided on an "as-is" basis and is believed to be correct, however any use of the information is your own responsibility.

This web-site may contain links to web-sites outside Poul Petersen domain ( www.poulpetersen.dk ).
Poul Petersen has no control over and assumes no responsibility for the content of any web-site outside Poul Petersen own domain.

Poul Petersen does not use cookies to "enhance your experience" on this website.

Poul Petersen, C/Faya 14, 35120 Arguineguín, Las Palmas, Spain.
E-mail: diy@poulpetersen.dk

Poul Petersen DIY index

Poul Petersen notes index

Copyright © Poul Petersen 2017. Last update: 20191029. Valid HTML!